An integrated circuit can include a large number of sequential elements that perform various logic functions such as mathematical operations. A clock signal may be used as a timing reference to synchronize data or logic operations performed by the sequential elements positioned at different locations in the integrated circuit.
A clock distribution network (CDN) distributes a clock signal to the sequential elements through different interconnect segments across the integrated circuit. The CDN must distribute the clock signal with accuracy, particularly when the frequency of the clock signal is high. Inaccuracy in the clock signal can result in one clock edge not arriving at a location in the integrated circuit relative to another clock edge. Two types of clock inaccuracy are referred to as clock “skew” and clock “jitter.” Clock “skew” is a difference in the time that the clock signal reaches different locations in the integrated circuit. Electromagnetic propagation delays, buffer delays in a distribution network, resistive-capacitive (RC) delays associated with various distribution lines in the distribution network, and variations in the manufacturing process, temperature gradients, power supply, and load capacitance all may cause clock “skew.” Clock “jitter” is a distortion in a cycle and phase difference of a clock signal accumulated over time, and clock “jitter” can be exacerbated by noise.